Virtualization is commonly used by memory systems in order to map non-contiguous physical memory addresses to a contiguous address space. An operating system manages the virtual address space, assigning blocks of virtual addresses to blocks of physical addresses. A hardware unit included in the processor, commonly known as a memory management unit (MMU), is configured to translate the virtual addresses into the correct physical addresses using a page table. The page table maps blocks of virtual addresses, called pages, to blocks of physical memory. Each page table entry for a virtual address range may include a base physical address that identifies the first address in a range of physical addresses corresponding to the virtual address range. The page table entry may also include various attributes associated with the page such as write protection bits, access tags, compression information, and so forth.
Various architectures define pages of varying sizes. For example, the ARMv7-x architecture specified for many ARM® Cortex processors, defines pages of 4 KB, 64 KB, 1 MB, and 16 MB using a two-level hierarchical page table. Some architectures (or operating systems) only allow a single page size of, for example, 4 KB. However some attributes associated with pages may apply to larger regions of memory than a single 4 KB page. Thus, storing such attributes inside each page table entry is redundant. Having smaller page sizes creates large page tables for the same address space and may cause more cache misses in the translation lookaside buffers (TLBs) (i.e., smaller page sizes means the same number of page table entries stored in the TLB corresponds to a smaller range of addresses). Fetching large page table entries for these smaller pages is inefficient. Thus, there is a need for addressing these issues and/or other issues associated with the prior art.